1. Field of the Invention
The present invention relates to a wiring board, a method of manufacturing the same, and a semiconductor device and, more particularly, to a technique of increasing the insulating reliability and manufacturing yield.
2. Description of the Related Art
FIG. 1 is a front view showing an arrangement of a chip-on-film (COF) semiconductor device according to a prior art. FIG. 2 is a side view corresponding to FIG. 1.
The COF semiconductor device comprises a wiring board 11. In this case, the wiring board 11 is formed from a polyimide film having a thickness of about 10 to 50 μm. Wiring 12 made of a copper layer having a thickness of about 5 to 10 μm are formed on the upper surface of the wiring board 11. In this case, to form the wiring 12, an undercoat metal layer of Cr, NiCr, or NiTi and a copper layer are continuously formed on the wiring board 11 to several hundred Å and several thousand Å (1 Å=10−8 cm), respectively, by vacuum deposition or sputtering. After that, a copper layer is formed on the wiring board 11 by electroless plating or electroplating without interposing any adhesive. A plating layer (not shown) of a low-melting metal such as tin or solder is formed on the surface of the wiring 12. One end of each wiring 12 serves as a connection terminal 12a. In this case, no device hole is formed in the semiconductor chip mounting region of the wiring board 11. The wiring board 11 has a surface opposing a semiconductor chip 13 all over the semiconductor chip mounting region. Bump electrodes 14 made of gold and formed at the periphery of the lower surface of the semiconductor chip 13 are bonded to the upper surfaces of the connection terminals 12a on the wiring board 11 by AuSn eutectic alloy so that the semiconductor chip 13 is mounted at a predetermined portion on the upper-surface-side of the wiring board 11. After that, the space formed between the semiconductor chip 13 and the wiring board 11 is filled with an insulating resin 15 (also called a sealing resin) such as an epoxy resin by a known side potting method. The insulating resin 15 is heated and cured, thereby completing the semiconductor device.
Jpn. Pat. Appln. KOKAI Publication No. 2001-210676 describes an example of the method of manufacturing the semiconductor device as shown in FIGS. 1 and 2.
To manufacture the semiconductor device shown in FIGS. 1 and 2, a bonding apparatus shown in FIG. 3 is prepared. In this bonding apparatus, a bonding tool 22 movable in the vertical direction is arranged above a stage 21 having a built-in heater (not shown). The semiconductor chip 13 is placed on the stage 21 with the bump electrodes 14 being directed upward. A clamp 23 clamps the wiring board 11 at the periphery of the region where the semiconductor chip 13 is to be mounted. The bonding tool 22 is moved downward.
The wiring board 11 has the lower surface opposing the semiconductor chip 13 all over the semiconductor chip mounting region. The wiring board 11 is set with its lower surface being directed to the upper surface of the semiconductor chip 13, i.e., with the surface having the wiring 12 being directed toward the semiconductor chip 13.
Next, the bump electrodes 14 of the semiconductor chip 13 and the connection terminals 12a of the wiring board 11 are aligned.
As shown in FIG. 4, for example, the stage 21 is moved upward to bring the bump electrodes 14 into contact with the connection terminals 12a. The bonding tool 22 is moved downward again. In this state, the stage 21 is heated to 350° C. to 450° C., and preferably, about 400° C. to heat the semiconductor chip 13. In addition, the bonding tool 22 is heated to 250° C. to 350° C., and preferably, about 300° C. and brought into direct contact with the upper surface of the wiring board 11 to press it. The bump electrodes 14 and the connection terminals 12a formed on the wiring board 11 are heated and pressed for about 1 to 3 sec. The bonding strength is increased by forming the interface in this way, as described in the prior art.
However, the conventional semiconductor device has the following problem.
In the semiconductor device shown in FIGS. 1 and 2, the semiconductor chip 13 is bonded while keeping the wiring board 11 flat. In this case, the distance between the wiring 12 and an edge Ed on the lower-surface-side of the semiconductor chip 13 is short. If the wiring board 11 deforms in bonding, the edge Ed on the lower-surface-side of the semiconductor chip 13 may short-circuit to the wiring 12 of the wiring board 11, as shown in FIG. 5.
This mechanism will be described by using a detailed example.
For example, assume that the semiconductor chip 13 having gold bumps is bonded to a 6 μm thick copper pattern formed on the wiring board 11 made of polyimide at a load of 100 N and a bonding temperature of 300° C. to 400° C. while the periphery of the chip mounting region is fixed by the clamp. At this time, the wiring board 11 is heated to the softening point of polyimide at the bonding temperature so that it is softened and pressed.
The connection terminals 12a are made of pure copper, like the copper leads formed on the wiring board 11, and therefore are excellent in ductility as a material property. The hardness is relatively low, and the rigidity is also low. The connection terminal 12a made of pure copper is as thin as 6 μm. The width is about 20 μm. Bonding to initial polyimide is done at about 1 kg/cm. Since the width of the connection terminal 12a after patterning is about 20 μm, the adhesion strength of the connection terminal 12a is about 2 g/pin, i.e., considerably low.
Assume that the semiconductor chip 13 having the bump electrodes 14 is bonded to the flexible wiring board 11 in the above-described state by the bonding method described in Jpn. Pat. Appln. KOKAI Publication No. 2001-210676, i.e., at a temperature of 300° C. to 400° C. higher than the softening point of polyimide and a pressure of 100 N or more for a bonding time of 1 to 3 sec. The connection terminals 12a sink into polyimide due to the bonding load and are going to stretch. However, the other end of each connection terminal 12a is fixed by the clamp 23 and therefore cannot move.
In addition, the adhesion strength between the copper leads and polyimide is low. Hence, the wiring 12 formed from the copper leads are deformed and bent upward near the connection terminal 12a, as shown in FIG. 5. In the worst case, the wiring 12 is peeled from the wiring board 11 made of polyimide to form a void Vd.
When the interconnection (to be also referred to as a “lead” hereinafter) 12 is deformed and bent near the connection terminal 12a, the following problems (1) to (4) rise.
(1) Sn or AuSn melted in bonding flows out along the lead 12 and separates from the bonding portion. Accordingly, the temperature decreases so that the fluidity of the melted Sn or AuSn solder diminishes, and a solder mass Sd is formed. If the melted solder amount is large, the solder sticks to the surface of the semiconductor chip 13 in the pressed state in bonding, resulting in degradation of outer appearance.
(2) The wiring 12 formed from a copper lead is deformed and bent upward near the connection terminal 12a. The wiring 12 is peeled from the wiring board 11 made of polyimide and is bent. For this reason, the lead 12 may electrically short-circuit to the edge (Ed) of the semiconductor chip 13.
(3) The lead 12 may partially be peeled from the wiring board 11 at the interface. Solder serving as the bonding material enters the interface and degrades the bonding strength.
(4) Since the lead 12 sinks into the wiring board 11, the lead 12 may be cut by the bump electrode 14. Alternatively, the lead 12 may crack and rupture as the initial crack grows during a reliability test such as a heat cycle test.
To solve the problems (1) to (4), in Jpn. Pat. Appln. KOKAI Publication No. 2001-210676, simultaneously as the semiconductor chip 13 is mounted on the upper surface of the wiring board 11, a part of the connection terminal 12a near the bonding portion to the bump electrode 14 and a part of the wiring board 11 corresponding to the vicinity of the bonding portion are deformed and spaced apart from the lower surface of the semiconductor chip 13. More specifically, a slant region is formed, in which the connection terminal 12a and wiring board 11 gradually become spaced apart from the semiconductor chip 13 from the bonding portion to the bump electrode 14 toward the outside of the semiconductor chip mounting region, thereby forming the lead 12. With this method, the distance from the edge Ed of the semiconductor chip 13 is ensured.
In this method, however, an infinite number of cracks have already been formed in the lead 12 in bonding. When lead forming is executed in the state shown in FIG. 4, the lead 12 surely ruptures.
As a solution without lead forming, Japanese Patent No. 3284916 describes a bonding method in which the bonding temperature of AuSn solder is set to 250° C. or less.
When the bonding temperature is decreased, the deformation amount of polyimide can be reduced. However, only AuSn is formed at the bonding portion in bonding at 300° C. or less, and no Cu interdiffusion occurs in the bonding interface, as described in Japanese Patent No. 3284916. Since AuSn is a fragile intermetallic compound, the bonding strength decreases. The chip is readily peeled off and cannot be bonded.